The high performance PLL is a high speed, low jitter frequency synthesizer, developed as an IP block to reduce time to market, risk, and cost in the development of Analog Front-End design. It can generate a stable high-speed clock from an ultra-wide input clock. With excellent supply noise immunity, the PLL is ideal for use in noisy mixed signal SoC environments. This PLL integrates a Phase Frequency Detector (PFD), a Low Pass Filter (LPF), a Voltage Controlled Oscillator (VCO), and other associated circuits. All fundamental building blocks and programmable dividers are integrated in the core.
The low-power Fractional-N/SSCG PLL addresses power-sensitive applications. It supports non-integer clock multiplication, programmable clock synthesis, on-the-fly clock tracking or fine tuning, and spread spectrum clock generation. Designed for digital logic processes, the PLL incorporates robust design techniques to operate reliably in noisy SoC environments, such as high-speed communication systems, low power consumer devices, and memory interfaces.
