Vendor: Innosilicon Technology Ltd Category: PLL

PLL

The high performance PLL is a high speed, low jitter frequency synthesizer, developed as an IP block to reduce time to market, ri…

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Overview

The high performance PLL is a high speed, low jitter frequency synthesizer, developed as an IP block to reduce time to market, risk, and cost in the development of Analog Front-End design. It can generate a stable high-speed clock from an ultra-wide input clock. With excellent supply noise immunity, the PLL is ideal for use in noisy mixed signal SoC environments. This PLL integrates a Phase Frequency Detector (PFD), a Low Pass Filter (LPF), a Voltage Controlled Oscillator (VCO), and other associated circuits. All fundamental building blocks and programmable dividers are integrated in the core.

The low-power Fractional-N/SSCG PLL addresses power-sensitive applications. It supports non-integer clock multiplication, programmable clock synthesis, on-the-fly clock tracking or fine tuning, and spread spectrum clock generation. Designed for digital logic processes, the PLL incorporates robust design techniques to operate reliably in noisy SoC environments, such as high-speed communication systems, low power consumer devices, and memory interfaces.

Key features

  • Supports frequencies from 1GHz to 3.2GHz for versatile applications
  • Low jitter performance
  • Supports Fractional mode to enable fine frequency resolution for precise tuning
  • Supports SSC mode to reduce EMI
  • Supports multiple frequencies and phases
  • Input reference clock frequency is supported ranging from 10MHz to 500MHz
  • Built-in lock detector to indicate the frequency lock state

Block Diagram

PLL block diagram

Benefits

  • Low power consumption
  • Low jitter
  • Wide frequency range
  • Small area

Applications

  • Microprocessors and Microcontrollers
  • FPGAs and ASICs
  • RF Transceivers
  • Serial Data Communication
  • Audio/Video Systems
  • Consumer Electronics
  • Automotive Electronics
  • Radar and Sonar Systems
  • IoT Devices
  • Advanced Driver Assistance Systems
  • Consumer Electronics

What’s Included?

  • GDSII
  • CDL Netlist (MG Calibre Compatible)
  • Functional Verilog Model
  • Liberty timing models (.lib)
  • LEF
  • Application Note

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
PLL
Vendor
Innosilicon Technology Ltd

Provider

Innosilicon Technology Ltd
HQ: China
Innosilicon is a world-class one-stop shop of high-speed interface IP and design services with 18 years of history. Having empowered hundreds of well-known customers including Qualcomm, AMD, Microsoft, Amazon, with all major process nodes covered across the world's top 6 foundries (TSMC/Samsung/GF/UMC/Intel/SMIC) from 55nm to 3nm, Innosilicon boasts over 1300 employees and is fully devoted to extending its leadership in delivering advanced IP and ASIC services. Our team offers unique IP such as HBM3E/2E Combo, GDDR7/6X/6 Combo, LPDDR5X/5/4X/4 Combo, DDR5 DIMM support, UCle Chiplet, various High-speed SerDes and HDMI2.1/eDP1.4 Combo, all with standard PHY and controller combinations as well as custom design options. Our outstanding innovation capabilities have been proven in high-performance computing, high-bandwidth memory, automotive, multimedia low-power IoT and other fields. We drastically improve our customer satisfaction and reduce time to market by offering our unique domain specific design platforms and flexible win-win business models.
Contact Innosilicon Technology Ltd

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is PLL?

PLL is a PLL IP core from Innosilicon Technology Ltd listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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