All Digital Phase Locked Loop

Overview

The iniADPLL is an all digital implementation of a phase locked loop. Plls are widely used in telecom applications for clock recovery, clock generation and clock supervision.

Different phase dtectors (FIFO fill level, phase erros, and so on) may be used and can be adapted to perfectely fit the application.

Key Features

All Digital Implementation
Linear Frequency Range from 0 to n MHz
Infinite Frequency Hold Time
Programmable Center Frequency
Programmable Filter Characteristics (Cut-Off Frequency, Loop Gain)
Adaptable Phase Detector
Structured, Synchronous HDL RTL Design
Gate Count: approximately 5000

Benefits

The all digital solutions needs no external components, is fully programmable and can be started already locked.
Other advantages are found where long time constants are required or where the loop filter have to be programmed depending on the current operation conditions.

Block Diagram

Deliverables

VHDL or Verilog RTL Source Code
Functional Testbench
Synthesys Script
Data Sheet
User Guide
Hotline Support by means of phone, fax and e-mail

Technical Specifications

Foundry, Node

Technology independent

Maturity

Proven in ASIC and FPGA Technologies

Availability

now

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