Clock Synthesizer IP

Compare 73 Clock Synthesizer IP from 17 vendors (1 - 10)

All Digital Fractional-N PLL for Performance Computing in UMC 40LP
- Fractional multiplication with frequency up to 4GHz
- Low jitter (< 10ps RMS)
- Small size (< 0.01 sq mm)
- Low Power (< 5mW)
Integer-N-PLL-based HF Frequency Synthesizer and Clock Generator with integrated Loop Filter and VCO
- This integer-N PLL synthesizes 3.3V-square-wave FVCO frequencies within the HF range from 2.424MHz up to 9.697MHz, by steps of 18.9393kHz, and provides one fourth of fVCO on two other outputs, FDEM and FDRV, which feature quadrature phase difference or no phase shift depending on the control bit PH_SEL.
- The PLL-locked state within ±0.08% of fVCO is signaled by a logic high level on the LOCK output.
ULP Clock-Generator - GLOBALFOUNDRIES 22FDX
- ABB-enabled, All-Digital PLL clock generator for ultra-low power clocking in highly energy efficient Systems on Chip
- The Ultra-Low Voltage Clock Generator is targeted at Systems on Chip (SoCs) employing advanced power management techniques.
- The robust, fully digital architecture allows operation in a wide voltage and frequency range. Unique fast lock and instant frequency change features maximize the energy efficiency of the targeted systems.
ULP 10MHz Clock-Generator - GLOBALFOUNDRIES 22FDX
- The All Digital Frequency Locked Loop (ADFLL) architecture is reduced to the minimum amount of hardware necessary to generate a 10 MHz clock
- High energy efficiency: Only 5 μW are consumed during operation
- A reference clock divider allows reference clock frequencies from 32 kHz to 1 MHz
MEMS-based Clock Generator with On-chip Temperature Compensation
- The MVCLK02 is a high-precision and programmable clock generator circuit, with a wide output frequency range.
- The chip contains a versatile MEMS oscillator circuit that is designed to ensure high performance for a wide range of MEMS resonators and with different parameters.
General-purpose & Specialized Ring PLLs + RTL-based Solutions
- Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
- Input & output frequency ranges greater than 1000:1
Programmable 6-bit CMOS frequency divider
- iHP SGB25V
- Range of dividing ratio 1…63
- Dividing ratio change with step 0.5
- Compact structure
Programmable CMOS frequency divider (56..16383 dividing ratio)
- iHP SGB25V
- Programmable dividing ratio (56..16383)
- Wide frequency range (50..1050 MHz)
- Small area
Programmable frequency divider (56 to 16383 dividing ratio)
- HP SGB25V
- Programmable dividing ratio (56 to 16383)
- Wide frequency range (50 to 1050 MHz)
- Small area
PLL CMOS phase-frequency detector with CMOS charge pump
- iHP SGB25V
- Input signals with low amplitude
- Low disbalance of output current
- Minimum disbalance of the charging/discharge current in loop filter capacitors