Achieving Yield in the Nanometer Age

Can you remember the first game you ever played? It probably had very few rules, very few actions and a straightforward path to success. As you grew older, your games became more complicated. Rules became more complex and possible actions increased. Determining the best move required you to evaluate multiple options and anticipate the actions of other players.

Integrated circuit design has followed a similar path. Early on, design rules were absolute and finite. The path to yield was fairly simple " comply with all the design rules, and yield would follow. Designers didn't need to worry too much about what happened in the fab after tape-out.

In the nanometer era, the game has changed. Yield success is much harder to achieve, because of the increased number and complexity of variables affecting manufacturability. The definition of yield itself has changed, now incorporating measures of variable power management, multi-modal performance and circuit integrity. The designer's strategy must shift from simple design rule compliance to the definition and design of the optimal layout for the highest yield.

The most obvious factor is the exponential explosion of feature count and design rules resulting from finer feature size and increasing interconnects (Figure 1). There are more DRC rules, and they are much more complex and often interdependent. Feature-based (systematic) defects are overtaking particle-based (random) defects as a cause of yield loss.

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