Verification methodologies keep pace with complex IP
By Roger Witlox, Ronald Heijmans and Chris Wieckardt, NXP Semiconductors
August 14, 2007 -- edadesignline.com
The verification of IP cores continues getting more complex and time consuming, especially processor cores, such as CPUs, floating-point units, and digital signal processors, the subject of this story. The challenge is to design and verify a new embedded vector processor with significant enhancements over its predecessor. This has been achieved by NXP's AdelanteTM VD3204x Embedded Vector DSP family.
In order to improve the quality of our DSP technology at DSP-IC, a department within NXP Semiconductors (formerly Philips Semiconductors), the attention for verification turned to tools and techniques that might advance the verification process. The experiences are shared in the coming paragraphs.
August 14, 2007 -- edadesignline.com
The verification of IP cores continues getting more complex and time consuming, especially processor cores, such as CPUs, floating-point units, and digital signal processors, the subject of this story. The challenge is to design and verify a new embedded vector processor with significant enhancements over its predecessor. This has been achieved by NXP's AdelanteTM VD3204x Embedded Vector DSP family.
In order to improve the quality of our DSP technology at DSP-IC, a department within NXP Semiconductors (formerly Philips Semiconductors), the attention for verification turned to tools and techniques that might advance the verification process. The experiences are shared in the coming paragraphs.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related Articles
- SoC Test and Verification -> ATE struggles to keep pace with VLSI
- Mixed Signal Design & Verification Methodology for Complex SoCs
- Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP
- Challenges and Benefits of Low Power Design Verification with CPF for a standalone IP
Latest Articles
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval