Today's DSP Design Challenge - Power Efficiency
By Hans Roeven and Norm Kelly
The most important design goal in new processor developments is power efficiency. With silicon implementation technologies scaling rapidly to 90nm and beyond, power consumption is a primary issue holding back SoC designers from integrating more functions on a single chip. In order to attack this problem when designing a new DSP, the best approach is a holistic one. This article will discuss how Synopsys and Phillips met the power efficiency challenge.
Click here to read more
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related White Papers
- New Power Management IP Solution Can Dramatically Increase SoC Energy Efficiency
- Breaking new energy efficiency records with advanced power management platform
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
- Reliability challenges in 3D IC semiconductor design
Latest White Papers
- RISC-V basics: The truth about custom extensions
- Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
- Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
- relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions