SystemVerilog Reference Verification Methodology: VMM Adoption
Thomas Anderson, Janick Bergeron and Eduard Cerny (Synopsys, Inc.) Alan Hunter and Andrew Nightingale (ARM Ltd.)
(09/04/2006 8:22 AM EDT), EE Times
The larger and more complex that system-on-chip (SoC) designs grow, the more verification dominates the development process. In fact, effective design reuse puts even more pressure on the verification team to reduce their part of the schedule. The best solution to this dilemma is the adoption and deployment of a reuse-oriented, coverage-driven methodology that yields more efficient verification, while also increasing the likelihood of first-silicon success.
This is the last in a series of four articles outlining a reference verification methodology that meets these goals for both RTL and system-level verification. This methodology is enabled by the SystemVerilog hardware design and verification language standard and is documented in the Verification Methodology Manual (VMM) for SystemVerilog, a book jointly authored by ARM and Synopsys. This article focuses on ways to adopt the VMM methodology and deploy it quickly throughout an entire SoC project.
(09/04/2006 8:22 AM EDT), EE Times
The larger and more complex that system-on-chip (SoC) designs grow, the more verification dominates the development process. In fact, effective design reuse puts even more pressure on the verification team to reduce their part of the schedule. The best solution to this dilemma is the adoption and deployment of a reuse-oriented, coverage-driven methodology that yields more efficient verification, while also increasing the likelihood of first-silicon success.
This is the last in a series of four articles outlining a reference verification methodology that meets these goals for both RTL and system-level verification. This methodology is enabled by the SystemVerilog hardware design and verification language standard and is documented in the Verification Methodology Manual (VMM) for SystemVerilog, a book jointly authored by ARM and Synopsys. This article focuses on ways to adopt the VMM methodology and deploy it quickly throughout an entire SoC project.
To read the full article, click here
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related Articles
- SystemVerilog reference verification methodology: Introduction
- SystemVerilog reference verification methodology: RTL
- SystemVerilog reference verification methodology: ESL
- Five Vital Steps to a Robust Testbench with DesignWare Verification IP and Reference Verification Methodology (RVM)
Latest Articles
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events
- A Reconfigurable Framework for AI-FPGA Agent Integration and Acceleration
- Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
- FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design