A system-level verification flow for EDA
Mike Stellfox, Cadence Design Systems
(03/19/2007 9:00 AM EDT), EE Times
The EDA industry continues to innovate and develop cutting-edge tools for the design and verification of hardware. But it has not yet found a way to accelerate growth within hardware/ software development or to capitalize on the interest around what Cadence calls enterprise system-level (ESL) solutions.
To create a solution that offers a true enterprisewide system-level flow, the industry must develop a comprehensive methodology that leverages much of the success we've seen in hardware development. This includes focusing on system-level creation, simulation, transformation, analysis, integration and verification. With continued innovation in those areas, focusing on how they relate to system-level development, we'll gain the power and flexibility needed to deliver on the vision of system-level verification.
(03/19/2007 9:00 AM EDT), EE Times
The EDA industry continues to innovate and develop cutting-edge tools for the design and verification of hardware. But it has not yet found a way to accelerate growth within hardware/ software development or to capitalize on the interest around what Cadence calls enterprise system-level (ESL) solutions.
To create a solution that offers a true enterprisewide system-level flow, the industry must develop a comprehensive methodology that leverages much of the success we've seen in hardware development. This includes focusing on system-level creation, simulation, transformation, analysis, integration and verification. With continued innovation in those areas, focusing on how they relate to system-level development, we'll gain the power and flexibility needed to deliver on the vision of system-level verification.
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- EDA focus shifts to system level design
- Accurate System Level Power Estimation through Fast Gate-Level Power Characterization
- HW/SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures
- The Challenges and Benefits of Analog/Mixed-Signal and RF System Verification above the Transistor Level
Latest Articles
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS