Synthesis-aware clock analysis and constraints generation

Jason Xing, Vice President of Engineering, ICScape Inc.
EETimes (5/6/2013 10:33 AM EDT)

Physical implementation challenges of clock nets

The intentions of a clock tree synthesis (CTS) tool are to create a balanced clock network with short insertion delay, smaller skews, and as few buffers as possible. Long clock insertion delays will create large on-chip variation (OCV) on clock network, which makes timing closure harder to accomplish. Large clock skews will add to the timing closure problem.

Clocks are fast-switching signals by design. In today’s SOC designs, the number and complexity of clock networks require a large number of buffers to sufficiently drive the clock signals around the chip, thereby increasing power consumption. This increase in power consumption is a major problem in wireless and handheld device markets, which are primarily driving today’s semiconductor market.

Modern SOC designs use complex clock structures, and the number of clock trees is growing from a handful to a few hundred. Prior to the availability of CTS, physical designers did not have adequate tools to analyze clock structures. Since CTS tools are not logically aware, clock constraints are used to optimize the clock graph that CTS will work on.

However, the number of clocks in today’s designs has exploded the complexity of clock constraint generation, which for the most part is a manual task. This often results in the generation of improper or non-optimal clock constraints, leading to post-CTS clock structures with long clock latency, large clock skew, and high buffer count.

In addition, modern SOC designs use advanced techniques such as multi-voltage domains to reduce chip power, and such structures make the balancing of clock networks very difficult.

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