Routing density analysis of ASICs, Structured ASICs, and FPGAs
Programmable Logic DesignLine
(10/19/2005 11:14 AM EDT)
This article uses well-known routing estimation techniques to analyze the trends of routing area requirements for standard cell ASICs, coarse-grained standard metal Structured ASICs, and field programmable gate arrays FPGAs. The cell granularity and the metal interconnect structure of these diametrically different architectures is analyzed and compared.
Standard cell ASICs typically feature fine-grained cell architectures. These devices have functions created out of standard single gate primitives, which are combined with custom metal interconnect, metal segments, and vias fabricated with custom masks. At the other end of the spectrum we find FPGAs, which are standard products with programmable elements that are used to connect predefined metal segments together with coarse-grained programmable cells.
Structured ASICs have regular arrays of coarse-grained programmable cells. Early Structured ASIC fabrics required multiple unique metal and via photomasks to fully implement a design. More recently, standard metal Structured ASICs have evolved. These devices comprise a sea of basic logic and memory building blocks coupled with a pre-configured, pre-characterized routing superhighway system. In the case of these standard metal fabrics, a single via layer - implemented using a single photomask or ebeam - is used to turn different routing paths on and off.
To read the full article, click here
Related Semiconductor IP
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- FH-OFDM Modem
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- PQC CRYSTALS core for accelerating NIST FIPS 202 FIPS 203 and FIPS 204
- USB Full Speed Transceiver
Related White Papers
- Improving ASIC Design Verification using FPGAs and Structured ASICs
- Single event effects (SEEs) in FPGAs, ASICs, and processors, part I: impact and analysis
- Structured ASICs rescue endangered species
- Structured ASICs allow improved design flow
Latest White Papers
- FastPath: A Hybrid Approach for Efficient Hardware Security Verification
- Automotive IP-Cores: Evolution and Future Perspectives
- TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models