Multi-core, multi-IP reduce development time for infotainment apps
By Matthias Wenzel, Renesas Technology Europe GmbH
embedded.com(11/04/09, 11:22:00 AM EST)
With its new SH7786, Renesas has introduced a new concept in modular multimedia processors and complete multimedia system solutions for the automotive industry. Single-chip and System-on-Chip (SoC) processors provide customers with scalable and integrated solutions within a single product family. The new range offers a multi-core and multi-IP design for increased scalability, a key consideration during software development. Renesas' goal with the new range is to keep customers' development cycles as short as possible while increasing performance with each new generation. This evolutionary approach, based on current architectures, ensures low-risk system integration. The established SH superscalar architecture has not been abandoned, but rather complemented and extended with a dual-core processor.
The SH7786 is the first dual-core processor in the SH4A family's CPU range and will be followed this year by a dual-core SOC, an evolution of the SH7775. Renesas Technology made an early decision to adopt multi-core technology and developed a prototype chip with four SH-4A CPU cores and maximum processing power of 4,320 MIPS at a clock frequency of 600 MHz.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- eFuse Controller IP
- Secure Storage Solution for OTP IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
Related Articles
- Choosing between dual and single core media processor configurations in embedded multimedia designs
- Selecting the right media processor for networked multimedia designs
- Managing the 8- to 32-bit processor migration
- Software Infrastructure of an embedded Video Processor Core for Multimedia Solutions
Latest Articles
- Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference
- Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor