Designing remote radio heads (RRHs) on high-performance FPGAs
Xiaofei Dong, Altera Corporation
2/7/2011 4:28 PM EST
Introduction
Current and future generations of wireless cellular systems feature heavy use of Remote Radio Heads (RRHs) in the base stations. Instead of hosting a bulky base station controller close to the top of antenna towers, new wireless networks connect the base station controller and remote radio heads through lossless optical fibers. The interface protocol that enables such a distributed architecture is called Common Publish Radio Interface (CPRI). With this new architecture, RRHs offload intermediate frequency (IF) and radio frequency (RF) processing from the base station. Furthermore, the base station and RF antennas can be physically separated by a considerable distance, providing much needed system deployment flexibility.
Typical advanced processing algorithms on RRHs include digital up-conversion and digital down-conversion (DUC and DDC), crest factor reduction (CFR), and digital pre-distortion (DPD). DUC interpolates base band data to a much higher sample rate via a cascade of interpolation filters. It further mixes the complex data channels with IF carrier signals so that RF modulation can be simplified.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related Articles
- FPGAs offer cost-effective, flexible solutions for remote radio heads
- High-Performance DSPs -> Software-defined radio infrastructure taps DSP
- Embedded Systems: Programmable Logic -> Common gateway networks enable remote programs
- Embedded Systems: Programmable Logic -> FPGAs don remote reprogram habits
Latest Articles
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension