Reducing energy cost of intra-chip communications

Fabien Clermidy, Ivan Miro-Panades, Yvain Thonnart and Pascal Vivet, CEA-Leti
EETimes (5/15/2012 8:08 AM EDT)

With the advent of new highly computing-intensive mobile applications (high throughput and software-defined radio, high-resolution video streaming, 3D image processing, augmented reality…), current system-on-chips (SoCs) are quickly moving towards many-cores for increasing parallelism. As a result, the number and distance of communications between these cores are growing exponentially. This point is explaining the relative importance of communications which can account for up to 30 percent of overall energy consumption in the highest performing many-core architectures.

From multi-cores to many-cores

For achieving high-performance systems, it is well-known that the race towards higher frequency has moved towards a race in terms of number of cores. This is true for desktop, but also for laptop, tablets and mobile phones with an even quicker evolution speed. Figure 1 shows a typical evolution of current SoCs: A multi-core host processor is used for sustaining the required performance for web applications while a sea of Processing Engines (PE) is used for sustaining highly parallel and computing-intensive applications. Then, each application will use parts of these PE in a configurable manner, while the corresponding software stack will run on the host processors.

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