PSL Verification Package for the Open Core Protocol
By Sami Maisniemi, Nokia
December 14, 2006 -- edadesignline.com
Introduction
Nokia utilizes the Open Core Protocol (OCP) as a standard interconnection architecture for its systems. So far there has not been a unified verification methodology for interconnections available. As a consequence, there was an obvious demand for a new verification package that fulfills the following requirements:
December 14, 2006 -- edadesignline.com
Introduction
Nokia utilizes the Open Core Protocol (OCP) as a standard interconnection architecture for its systems. So far there has not been a unified verification methodology for interconnections available. As a consequence, there was an obvious demand for a new verification package that fulfills the following requirements:
- The package verifies the compatibility of the interconnection with the OCP standard.
- The package can be installed with minimal efforts without modifying the existing verification environment.
- The package can be configured with minimal efforts without access to the source code.
- The package is compatible with the existing design and verification flows.
- No previous knowledge of assertion-based verification or hardware property languages is required.
- No additional EDA tools are required.
- The package must be cost-effective in terms of maintenance and support.
To read the full article, click here
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
Related Articles
- IP core-centric communications protocol Introducing Open Core Protocol 2.0
- Better Products, Happier Customers with Current-Based Simulation/Verification and the Open Core Protocol
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
Latest Articles
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
- A 129FPS Full HD Real-Time Accelerator for 3D Gaussian Splatting
- SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation
- TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks