PSL Verification Package for the Open Core Protocol
December 14, 2006 -- edadesignline.com
Introduction
Nokia utilizes the Open Core Protocol (OCP) as a standard interconnection architecture for its systems. So far there has not been a unified verification methodology for interconnections available. As a consequence, there was an obvious demand for a new verification package that fulfills the following requirements:
- The package verifies the compatibility of the interconnection with the OCP standard.
- The package can be installed with minimal efforts without modifying the existing verification environment.
- The package can be configured with minimal efforts without access to the source code.
- The package is compatible with the existing design and verification flows.
- No previous knowledge of assertion-based verification or hardware property languages is required.
- No additional EDA tools are required.
- The package must be cost-effective in terms of maintenance and support.
The purpose of the assertion-based verification (ABV) method is to convert functional features of a specification into explicit assertions that define the behavior of logic over time. The hardware property languages differ remarkably from the hardware description and verification languages. Instead of implementing a test bench, the hardware property languages are utilized to implement assertions. The property specification language (PSL) is a vendor independent hardware property language that has been standardized by the IEEE. The purpose of the PSL is not to replace, but to complement the existing verification methodologies like VHDL and Verilog test benches. The goal is to improve both verification quality and efficiency.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related White Papers
- IP core-centric communications protocol Introducing Open Core Protocol 2.0
- Better Products, Happier Customers with Current-Based Simulation/Verification and the Open Core Protocol
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
Latest White Papers
- RISC-V basics: The truth about custom extensions
- Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
- Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
- relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions