Power verification: trust but verify, or verify and trust?
Jerry Frenkil, Sequence Design
EE Times (07/13/2009 12:00 AM EDT)
The issue of verification has never been larger. Today, functional verification is at least as big a task as design and, in many cases, much larger. This has been the case for awhile now and the situation doesn't appear to be changing any time soon. If anything, verification is becoming an even larger and more difficult task.
It isn't hard to see why. More transistors and larger die sizes result in greater complexity. It is common today to see single chips with multiple CPUs and multiple memory systems, a DSP, and various interfaces such as USB, 802.11, and Bluetooth not to mention a healthy smattering of analog functions. And don't forget power management.
Accompanying all of the increased complexity is increased power consumption although, thanks to designer creativity, power consumption has not increased as rapidly as functional complexity. Various types of power reduction techniques have been employed to keep power concerns from derailing functional aspirations. After all, what good is a shiny new phone with video capabilities if the battery life is measured in minutes instead of hours or days?
EE Times (07/13/2009 12:00 AM EDT)
The issue of verification has never been larger. Today, functional verification is at least as big a task as design and, in many cases, much larger. This has been the case for awhile now and the situation doesn't appear to be changing any time soon. If anything, verification is becoming an even larger and more difficult task.
It isn't hard to see why. More transistors and larger die sizes result in greater complexity. It is common today to see single chips with multiple CPUs and multiple memory systems, a DSP, and various interfaces such as USB, 802.11, and Bluetooth not to mention a healthy smattering of analog functions. And don't forget power management.
Accompanying all of the increased complexity is increased power consumption although, thanks to designer creativity, power consumption has not increased as rapidly as functional complexity. Various types of power reduction techniques have been employed to keep power concerns from derailing functional aspirations. After all, what good is a shiny new phone with video capabilities if the battery life is measured in minutes instead of hours or days?
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related Articles
- Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP
- Challenges and Benefits of Low Power Design Verification with CPF for a standalone IP
- Robust Low power Architecture verification Strategy
- Integrated Low Power Verification Suite: The way forward for SoC use-case Verification
Latest Articles
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval