Planning reset strategy: Flow & functionality in OVC
Parag Goel, Pushkar Naik, Applied Micro Circuits Corp.
3/9/2011 8:01 AM EST
Overview
Reset strategy, which has long been a part and parcel of the design methodology, playing a vital role in the successful working of any given design, has become increasingly important on the verification methodology front. Reset forms a fundamental property of any protocol/system and is the first step in the sequence of operations done for any system bring up. The following write-up addresses this essential strategy to be followed during verification using an OVM-based test bench.
While developing an OVM–based IP (i.e. OVM Verification Component (OVC)), it is required to get a clear perspective on the way it behaves and recovers from reset application during the course of simulation.
To read the full article, click here
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Digital PUF IP
Related White Papers
- SoC tool flow techniques for detecting reset domain crossing problems
- An Automated Flow for Reset Connectivity Checks in Complex SoCs having Multiple Power Domains
- Optimizing Floorplan for STA and Timing improvement in VLSI Design Flow
- Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures
Latest White Papers
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
- How Mature-Technology ASICs Can Give You the Edge
- Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY