Optimizing efficiency and flexibility in DSP systems
Mouna Elkhatib and Sverrir Olafsson, Conexant
EDN (January 13, 2013)
For as long as multipliers have been implemented in silicon, DSP (digital signal processing) devices have been developed to solve problems in audio, video, communications and a variety of other applications. In many cases the DSP algorithms have been implemented directly in dedicated customized logic to achieve an optimal solution. In others, generic programmable DSPs have been utilized to provide a flexible platform to implement algorithms in firmware. Increasingly, GPPs (general purpose processors) and CPUs (central processing units) have acquired capabilities to realize DSP algorithms, offering a platform to mix non-DSP functions like network stacks with complex DSP algorithms on the same CPU.
This article will explore the tradeoffs leading designers to these different design choices. Typically, well understood algorithms of limited complexity are implemented in dedicated hardware, whereas less rigid complex algorithms requiring multiple algorithm steps are implemented on programmable DSPs. If the application requires non-DSP algorithms, such as USB or network protocols, the choice becomes between a GPP and a DSP, where the ratio of DSP calculations to generic (e.g. protocol) computation will typically determine the outcome.
To read the full article, click here
Related Semiconductor IP
- HiFi iQ DSP
- 5G IoT DSP
- 5G RAN DSP
- Tensilica ConnX 120 DSP
- 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)
Related Articles
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
- Role of Embedded Systems and its future in Industrial Automation
- Audio Validation in Multimedia Systems and its Parameters
- Optimizing Communication and Data Sharing in Multi-Core SoC Designs
Latest Articles
- GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon
- Creating a Frequency Plan for a System using a PLL
- RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs
- MING: An Automated CNN-to-Edge MLIR HLS framework
- Fault Tolerant Design of IGZO-based Binary Search ADCs