Multiband architecture for high-speed SerDes
Christian Weber, Jinjin He, Lizhi Charlie Zhong, and Huaping Liu
EETimes (1/20/2011 3:45 AM EST)
Abstract
As the speed of serializer/deserializer (SerDes) increases (e.g., to 25 Gbps and above), the channel will cause more severe inter-symbol interference. Design of low-complexity transceivers for such high-speed SerDes faces many technical challenges. In this paper, we explore a multiband architecture for a 25 Gbps SerDes, where the channel in each sub-band is approximately frequency flat, eliminating need of an equalizer in the receiver. Since different bands experience different signal attenuations, the power level for each band can be adjusted accordingly to minimize the average transmission power. A multiband transceiver is designed, and analysis and simulation results for various choices of parameters (bands, modulations, etc.) are presented.
To read the full article, click here
Related Semiconductor IP
- RVA23, Multi-cluster, Hypervisor and Android
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- H.264 Decoder
Related White Papers
- How to cut power consumption for high-speed apps with A/D converter architecture
- Meet the SERDES challenge: Design a high-speed serial backplane
- What's in the Future for High-Speed SerDes?
- Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs
Latest White Papers
- RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design
- CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance