Methodology for advanced flip-chip ASICs

Javier A. DeLaCruz, eSilicon Corp
(11/21/2005 10:00 AM EST)
EE Times

For decades, chips have been designed in isolation of their respective packages. This methodology does not work for large ASICs and certainly will not work for large flip-chip packages (greater than 17 mm per side); these require a more holistic approach that considers key elements of the overall design, such as die exit routing on the package, layer assignments, bump assignments, signal integrity, routability and pc-board signal integrity.

While custom packages for larger ASICs incur larger initial startup costs, they consistently deliver lower unit costs than standard options with predetermined footprints, because the design team can use the smallest die size that will handle the interconnects and/or core-logic limitations. And whereas standard packages must be designed to support all possible connection types, custom packages can be tailored to improve performance. Differential lines, which are typically implemented in standard packages as similarly routed trace lengths, can be routed in custom packages as true 100-ohm pairs. Complex group delay buses can be length-matched relative to each other and to their clocks.

See image: A sample single-layer exit route pattern in a buildup package is shown. Bumped vias are seen at the far left of the image.

This article focuses on organic buildup routing, the predominant methodology for large flip-chip ASIC packages. It's important to note that most signal routing occurs in the upper layers of a buildup substrate, because the core vias' large size inhibits routability.

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