Interfacing QDR-II+ Synchronous SRAM with high-speed FPGAs, part 2
Reshmi Ravindran, Cypress Semiconductor
EETimes (9/17/2012 3:36 PM EDT)
Part 1 of this article discussed the hardware aspects required for interfacing QDRII+ memory with an FPGA. Part 2 deals with implementation of the QDR II+ controller in popular FPGAs using standard IP blocks.
Implementation of memory interfaces on FPGAs, especially for high-speed memories, was a tedious process until most of the FPGA vendors started providing configurable memory controller IP, such as the Xilinx Memory Interface Generator (MIG) tool and Altera’s QDR controller Megacore functions. These IP libraries are expensive and are not available with all variants of the FPGAs, however. Fortunately, alternatives exist. Most high-speed FPGAs offer standard IP blocks that can be configured and integrated to build a custom memory controller. This enables designers to develop memory controllers for their application and allows them to customize it suitably. Understanding the timing diagram of QDRII+ is essential for the controller implementation. Let’s take a closer look.
To read the full article, click here
Related Semiconductor IP
- Single Rail SRAM GLOBALFOUNDRIES 22FDX
- Dual Rail SRAM Globalfoundries 22FDX
- SRAM Test and Repair Solution
- SRAM Test and Repair Solution
- SRAM Test Solution
Related White Papers
- Choosing the right synchronous SRAM for your application
- How to power FPGAs with Digital Power Modules
- Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs
- Consumer IC Advances -> Set- top box SoC ready for high-speed demands
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design