How to power FPGAs with Digital Power Modules
Felix Martinez, Intersil Corporation
EDN (September 13, 2015)
The proliferation of voltage input rails for delivering point-of-load (POL) power to FPGAs is making power supply designs ever more challenging. As a result, encapsulated power modules are seeing increased use in telecom, cloud computing and industrial equipment because they operate as self-contained power management systems. They are easier to use than discrete solutions and speed time-to-market for both experienced and novice power-supply designers. Modules include all of the major components -- PWM controller, FETs, inductor and compensation circuitry -- with only the input capacitor and output capacitor needed to create an entire power supply.
This article discusses a FPGA reference design generator and walks you through the steps for selecting an FPGA, required power rails, backplane and digital power modules for POL. We will highlight a graphical user interface (GUI) that configures, validates and monitors the FPGA’s power supply architecture, and we will explain the GUI’s sequencing feature to power up the voltage rails, and select the power sequence order and rise and fall times.
To read the full article, click here
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related White Papers
- How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power
- BCD Technology: A Unified Approach to Analog, Digital, and Power Design
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS