Implementing an FPGA-based scalable OFDMA engine for WiMAX

Scalable orthogonal frequency-division multiple access (OFDMA) is a key physical layer component associated with mobile WiMAX. It is an enabling technology for future broadband wireless protocols including 3GPP and 3GPP2 and their long-term evolution.

The underlying nature of OFDMA is ideal for an FPGA-based WiMAX basestation design PHY. By leveraging a scalable OFDMA engine, engineering teams can save up to 18 months of development time. FPGA building blocks include bit-level, OFDMA symbol-level and digital intermediate frequency processing blocks.

Symbol mapping and demapping are used in bit-level processing, as well as forward error correction (FEC) based on Reed-Solomon and Viterbi MegaCore functions. FEC schemes such as convolution turbo codes from third-party vendors can be used as well. OFDMA symbol-level processing includes subchannelization and de-subchannelization.

Fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) MegaCore functions support cyclic prefix insertion. Digital IF processing includes single- and multiple-antenna digital up converters (DUCs), digital down converters (DDCs), advanced crest factor reduction (CFR), and digital pre-distortion (DPD). The IF modem package allows easy and efficient multi-channel and time-multiplexed implementations.

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