Implementing an FPGA-based scalable OFDMA engine for WiMAX
Akshaya Trivedi, Altera
(08/21/2007 10:45 AM EDT) -- EE Times
Scalable orthogonal frequency-division multiple access (OFDMA) is a key physical layer component associated with mobile WiMAX. It is an enabling technology for future broadband wireless protocols including 3GPP and 3GPP2 and their long-term evolution.
The underlying nature of OFDMA is ideal for an FPGA-based WiMAX basestation design PHY. By leveraging a scalable OFDMA engine, engineering teams can save up to 18 months of development time. FPGA building blocks include bit-level, OFDMA symbol-level and digital intermediate frequency processing blocks.
Symbol mapping and demapping are used in bit-level processing, as well as forward error correction (FEC) based on Reed-Solomon and Viterbi MegaCore functions. FEC schemes such as convolution turbo codes from third-party vendors can be used as well. OFDMA symbol-level processing includes subchannelization and de-subchannelization.
Fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) MegaCore functions support cyclic prefix insertion. Digital IF processing includes single- and multiple-antenna digital up converters (DUCs), digital down converters (DDCs), advanced crest factor reduction (CFR), and digital pre-distortion (DPD). The IF modem package allows easy and efficient multi-channel and time-multiplexed implementations.
(08/21/2007 10:45 AM EDT) -- EE Times
Scalable orthogonal frequency-division multiple access (OFDMA) is a key physical layer component associated with mobile WiMAX. It is an enabling technology for future broadband wireless protocols including 3GPP and 3GPP2 and their long-term evolution.
The underlying nature of OFDMA is ideal for an FPGA-based WiMAX basestation design PHY. By leveraging a scalable OFDMA engine, engineering teams can save up to 18 months of development time. FPGA building blocks include bit-level, OFDMA symbol-level and digital intermediate frequency processing blocks.
Symbol mapping and demapping are used in bit-level processing, as well as forward error correction (FEC) based on Reed-Solomon and Viterbi MegaCore functions. FEC schemes such as convolution turbo codes from third-party vendors can be used as well. OFDMA symbol-level processing includes subchannelization and de-subchannelization.
Fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) MegaCore functions support cyclic prefix insertion. Digital IF processing includes single- and multiple-antenna digital up converters (DUCs), digital down converters (DDCs), advanced crest factor reduction (CFR), and digital pre-distortion (DPD). The IF modem package allows easy and efficient multi-channel and time-multiplexed implementations.
To read the full article, click here
Related Semiconductor IP
- IEEE 802.16 WirelessMAN OFDM Channel Codec
- OFDM - Orthogonal Frequency Division Multiplexing
- Programmable OFDM Channel Estimator
- OFDM synchronization unit
- High Throughput Rate OFDM Baseband PHY Processor
Related Articles
- Tap into the advantages of a scalable OFDMA engine for WiMAX
- Safety Integrity Level - an Overview for FPGA Engineers
- Digital Associative Memories Based on Hamming Distance and Scalable Multi-Chip Architecture
- Designing FPGA Based Reliable Systems Using Virtex-5 System Monitor
Latest Articles
- System-Level Isolation for Mixed-Criticality RISC-V SoCs: A "World" Reality Check
- CVA6-CFI: A First Glance at RISC-V Control-Flow Integrity Extensions
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
- In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design