IC mixed-mode verification: The Sandwiched-SPICE approach
Garima Jain (Freescale)
EDN -- October 21, 2014
RTL- and SPICE-based mixed-signal verification means picking SPICE view for a number of modules (those involved in the concerned test case), and behavioral models for the remaining modules. As analog front-end modules get more complex, AMS verification has become even more challenging.
The limitations to be considered are as follows:
- The number of transistors the module taken in SPICE can have, or,
- The number of fast toggling signals (high frequency clocks etc.) which can be in the module to have reasonable run time.
The case may be such that the number of transistors is acceptable and there are just a couple of fast toggling signals. But what if this is not so? What if the number of fast toggling signals is large, or the netlist size of the module whose SPICE view is being picked is large, or both?
To read the full article, click here
Related Semiconductor IP
- EMFI Detector
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
Related White Papers
- IC design: A short primer on the formal methods-based verification
- Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP
- Out of the Verification Crisis: Improving RTL Quality
- Differentiation Through the Chip Design and Verification Flow
Latest White Papers
- On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions