IC mixed-mode verification: The Sandwiched-SPICE approach
Garima Jain (Freescale)
EDN -- October 21, 2014
RTL- and SPICE-based mixed-signal verification means picking SPICE view for a number of modules (those involved in the concerned test case), and behavioral models for the remaining modules. As analog front-end modules get more complex, AMS verification has become even more challenging.
The limitations to be considered are as follows:
- The number of transistors the module taken in SPICE can have, or,
- The number of fast toggling signals (high frequency clocks etc.) which can be in the module to have reasonable run time.
The case may be such that the number of transistors is acceptable and there are just a couple of fast toggling signals. But what if this is not so? What if the number of fast toggling signals is large, or the netlist size of the module whose SPICE view is being picked is large, or both?
To read the full article, click here
Related Semiconductor IP
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
Related Articles
- IC design: A short primer on the formal methods-based verification
- Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP
- Out of the Verification Crisis: Improving RTL Quality
- Differentiation Through the Chip Design and Verification Flow
Latest Articles
- VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems
- A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators
- Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks