How to achieve faster compile times in high-density FPGAs
January 17, 2007 -- pldesignline.com
With FPGA design complexity outpacing CPU speed, FPGA designers are more dependent on design tools and methodologies that speed compile times.
Over the last eight years there has been a 30× increase in logic density and memory bits in FPGA devices. The largest FPGAs – such as the recently announced Stratix III EP3SL340 from Altera – contain up to 338,000 equivalent logic elements (LEs) and more than 17 Mbits of embedded memory.
This rapid increase in logic density translates to an even larger increase in computing requirements for design compilation and place and route. Unfortunately, CPU speed has only increased by a factor of 11× during the same period. With FPGA design complexity outpacing CPU speed, FPGA designers are more dependent on design tools and methodologies that speed compile times and allow them to iteratively and efficiently debug, add features, and close timing. This article presents a three-stage methodology to increase productivity for engineers designing with high-end FPGAs.
To read the full article, click here
Related Semiconductor IP
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
Related White Papers
- How to achieve better IoT security in Wi-Fi modules
- Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs
- How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity
- How to manage changing IP in an evolving SoC design
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design