Reducing Power in Embedded Systems by Adding Hardware Accelerators

The rule of thumb in embedded system design has been that adding hardware increases power demands. The careful use of hardware accelerators, however, inverts the rule: adding hardware can reduce power.

By analyzing algorithms and implementing appropriate accelerators in programmable logic, developers can increase a design's performance while reducing power consumption in an embedded computing system.

Test results show that accelerators extend tradeoff options from as much as 200-fold performance improvement for the same power to the same performance with a 90% power reduction.

Programmable logic has, somewhat undeservedly, maintained a reputation from its early history as being a power-hungry approach to logic design. The rules of thumb have been that power consumption in an integrated circuit is roughly proportional to the chip's area for a given process technology, and a design implemented in programmable logic tends to be larger than if implemented in hard-wired logic. But these two factors, although suggestive, are misleading.

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