Viewpoint: The importance of FPGA-to-ASIC solutions to accelerate CPU-based protocols
By Joe Rash, CebaTech
pldesignline.com (March 03, 2010)
For many years, there has been a running debate about how to best handle the processing of protocols mid-way up the protocol stack in a data networking or enterprise storage application. Oftentimes this is array of protocols is referred to as the data management layer. Algorithms in the data management layer typically include protocols such as encryption, compression, hashing, and complex searching.
For flexibility reasons, many system designs stick with off-the-shelf CPUs such as an Intel or AMD x86 processor running on a standard server motherboard. Other CPU-centric solutions deploy more embedded solutions using multi-function CPUs such as Freescale's Power QUICC processor, which resides on a plug-in PCI Express-based card. While these CPU solutions certainly provide flexibility, they often fall short of meeting high-end performance targets within the constraints of a product's cost and power budget.
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- IP core-centric communications protocol Introducing Open Core Protocol 2.0
- Choose carefully your industrial-strength comms protocol
- Rapid Protocol Stack Development Framework
- Designing Using the AMBA (TM) 3 AXI (TM) Protocol -- Easing the Design Challenges and Putting the Verification Task on a Fast Track to Success
Latest Articles
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS