Building FPGA-based digital downconverters with graphical design tools
Ryan Verret, National Instruments
EETimes (12/8/2010 11:11 AM EST)
High bandwidth digital downconverters (DDCs) are critical components in many high-performance systems, including receivers of modulated communications, medical imaging devices, and low-level RF control hardware for scientific research.
Modern graphical programming tools and commercial, off-the-shelf hardware have progressed to the point that they can be used to implement high-performance designs with minimal FPGA-specific knowledge. A number of such high-level and graphical design tools exist, along with a variety of FPGA-based I/O hardware.
To read the full article, click here
Related Semiconductor IP
- USB 20Gbps Device Controller
- AGILEX 7 R-Tile Gen5 NVMe Host IP
- 100G PAM4 Serdes PHY - 14nm
- Bluetooth Low Energy Subsystem IP
- Multi-core capable 64-bit RISC-V CPU with vector extensions
Related White Papers
- FPGAs: Embedded Apps : Designing an FPGA-based network communications device
- FPGAs: Embedded Apps : FPGA-based FFT engine handles four times more input data
- FPGA-Based DPLL Approach Delivers Wide-Lock Range
- A Real-Time Image Processing with a Compact FPGA-Based Architecture
Latest White Papers
- CRADLE: Conversational RTL Design Space Exploration with LLM-based Multi-Agent Systems
- On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs