Emulator, accelerator, prototype - what’s the difference?
Brian Bailey
EETimes (11/1/2010 4:45 PM EDT)
In a previous blog, I talked about the confusion that seems to exist about the similarities and differences between emulators, accelerators and prototypes. In that blog I talked about what makes a prototype unique, and said I would come back to the issue of emulators and accelerators, so here we are.
First off, most of the time, as a user, you don’t really care. The differences are in the internals of how they are implemented, and this may affect the features they make available, but for the most part the confusion is created by the manufacturers of these devices so that they can say they are #1, or unique, or have highest capacity or speed or whatever. Let’s cut through all of that and look at what is fundamentally different. There is an umbrella term for all of them which is hardware assisted verification.
To read the full article, click here
Related Semiconductor IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
Related Articles
- Increasing visibility in FPGA prototypes and emulators
- A silicon virtual prototype is key in achieving design closure
- SoCs need logical virtual prototype
- Build Complex ASICs Without ASIC Design Expertise, Expensive Tools - Take advantage of an architecture comparable to your original FPGA prototype design by migrating to a structured ASIC
Latest Articles
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
- In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events