Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 3

By Scott Schaefer, Micron Technology
Embedded.com (11/25/08, 03:40:00 PM EST)

Clock Jitter and Statistics

As previously discussed in Part 1 and Part 2 in this series, measured DDR2/DDR3 clock jitter values are not absolute, but the specification limits are. This presents a problem: is the measured clock jitter a passing value if it is not violating the absolute specification limit? This is unlikely since clock jitter is a random event and it is not possible to measure the worst-case clock jitter event. So, whether a measured value is passing or failing depends on several factors.

Recall that if the clock jitter specifications are violated, the clock jitter's adverse effect on the input timings can be neutralized by increasing the clock period. This suggests that the clock jitter value itself is not the issue; the issue is how much the input timing is adversely affected by the clock jitter.

Also as previously mentioned, until a statistically sound standard deviation (sigma, s) value for the clock jitter is obtained, the clock jitter investigation is incomplete. A statistically sound standard deviation value depends on two factors: (1) the sample size used to measure the clock jitter; and (2) the system BER target.

When investigating clock jitter statistically, only the negative clock jitter only needs to be looked at. For device functionality concerns, the DRAM is adversely affected by negative clock jitter violations, not positive clock jitter violations.

And when the output timings are evaluated, the positive clock jitter results should mirror the negative clock jitter results. Additionally, since the clock jitter is Gaussian, all the clock jitter values should track each other. Analyzing tJITper and how it is compensated for generally ensures that the other clock jitter specifications will not be an issue.

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