Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 1

Prior to DDR2 technology, the expectation was that clock jitter specifications could be absorbed by the DRAM timing specifications. DDR2's faster clock rates and on-chip delay locked loop (DLL) changed all that, and industry-standard clock jitter specifications became a requirement for users and suppliers, and some, such as Micron, actually started specifying clock jitter specifications with the release of DDR memory.

Despite the fact that there seemed to be enough timing margin with DDR, the inclusion of the DLL begged for clock jitter guidance. Now, even though both DDR2 and DDR3 have clock jitter specifications, few DRAM users understand how to apply them or how to determine if their system clock violates the specification limits and what action to take if it does.

This series of three articles explores DDR2/DDR3 clock jitter specifications and provides guidance to embedded systems developers on how to apply them and how to deal with violations since many systems will unintentionally encounter them. (Note that statements made are equally applicable to DDR2 and DDR3 SDRAM, unless stated otherwise.)

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