Are design and test conflicting or symbiotic?
Arif Samad, Synopsys
EEtimes (10/20/2010 2:32 AM EDT)
These days, IC design engineers have more functionality to implement in their designs than ever before, even though design schedules are shrinking. Although design-for-test (DFT) is absolutely necessary to enable thorough and cost-effective manufacturing test, it potentially makes the overall design process even more challenging.
The paradigm of the designer “throwing the design over the wall” to the test engineer was viable in the days when DFT was limited to adding scan chains to a design, and timing delays of the signal propagation across gates were relatively greater than across the interconnects. But the old paradigm no longer applies in an era where advanced DFT methodologies are necessary to limit test cost, interconnect delays are dominant and power consumption critical.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related White Papers
- SoCs lend momentum to design-for-test solutions
- SOC: Submicron Issues -> Physics dictates priority: design-for-test
- DFT – IP Reuse & SoC
- DFT for SoC : The Economic Myths
Latest White Papers
- FeNN-DMA: A RISC-V SoC for SNN acceleration
- Multimodal Chip Physical Design Engineer Assistant
- Attack on a PUF-based Secure Binary Neural Network
- BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
- FD-SOI: A Cyber-Resilient Substrate Against Laser Fault Injection—The Future Platform for Secure Automotive Electronics