Design considerations for power sensitive embedded devices
Adam Kaiser, Mentor Graphics
EETimes (4/17/2012 10:38 PM EDT)
The importance of power management and optimization in today’s embedded designs has been steadily growing as an increasing number of battery-powered devices continue to perform more complex tasks.
The unrelenting demand for connectivity and new features presents a growing challenge to designers. Yet, very often power optimizations are left to the very end of the project cycle, almost as an afterthought. When setting out to design a power-optimized embedded device, it is important to consider power management from the very inception of the project.
This article discusses design considerations that should be made when beginning a new embedded design. The considerations include choosing the hardware with appropriate capabilities, defining hardware design constraints to allow software to manage power, making the right choice of an operating system and drivers, defining appropriate power usage profiles, choosing measurable power goals, and providing these goals to the software development team to track throughout the development process.
To read the full article, click here
Related Semiconductor IP
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
- Neuromorphic Processor IP
Related White Papers
- The evolution of embedded devices: Addressing complex design challenges
- Deciphering phone and embedded security - Part 4: Ideal platform for next-generation embedded devices
- Memory solution addressing power and security problems in embedded designs
- Simplify the Internet of Things connectivity of embedded devices
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS