Design considerations for power sensitive embedded devices
Adam Kaiser, Mentor Graphics
EETimes (4/17/2012 10:38 PM EDT)
The importance of power management and optimization in today’s embedded designs has been steadily growing as an increasing number of battery-powered devices continue to perform more complex tasks.
The unrelenting demand for connectivity and new features presents a growing challenge to designers. Yet, very often power optimizations are left to the very end of the project cycle, almost as an afterthought. When setting out to design a power-optimized embedded device, it is important to consider power management from the very inception of the project.
This article discusses design considerations that should be made when beginning a new embedded design. The considerations include choosing the hardware with appropriate capabilities, defining hardware design constraints to allow software to manage power, making the right choice of an operating system and drivers, defining appropriate power usage profiles, choosing measurable power goals, and providing these goals to the software development team to track throughout the development process.
To read the full article, click here
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
Related Articles
- Deciphering phone and embedded security - Part 4: Ideal platform for next-generation embedded devices
- Memory solution addressing power and security problems in embedded designs
- Simplify the Internet of Things connectivity of embedded devices
- Power management in embedded software
Latest Articles
- RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
- Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
- A 129FPS Full HD Real-Time Accelerator for 3D Gaussian Splatting
- SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation
- TensorPool: A 3D-Stacked 8.4TFLOPS/4.3W Many-Core Domain-Specific Processor for AI-Native Radio Access Networks