Data storage in non-volatile memory
Colin Walls, Mentor Graphics
EDN (November 23, 2014)
Although flash and other non-volatile memory technologies are widely used to implement embedded file systems, this may be too complex for some embedded applications. In many cases the memory may be most efficiently used as data structures that have been pre-initialized. This approach requires some management of data integrity. This article introduces the challenges and offers some simple solutions to using NVRAM.
Introduction to NVRAM
In a modern computer system, there is a large amount of memory. Most of it is the anachronistically named random access memory (RAM). The name makes little sense, as all memory is random access nowadays. When engineers talk about RAM, they mean volatile semiconductor memory, which can be written to and read from indefinitely so long as power is applied. It was not always like this. In the early days of computers, the most common form of program/data storage was “core memory”. This was, by modern standards, bulky and heavy (not to mention expensive!), but had a useful characteristic: it was non-volatile. Power was required to read or write data, but was not needed to retain it. With the core memory powered down, data would remain unchanged for indefinite periods of time. Interestingly, dropping or vibrating core memory could corrupt its contents, but this was rarely a cause for concern (except in earthquake zones) because computers were far from portable.
To read the full article, click here
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related White Papers
- Serial ATA and the evolution in data storage technology
- DDR3 memory interface controller IP speeds data processing applications
- Selecting the right Nonvolatile Memory IP: Applications and Alternatives
- Argument for anti-fuse non-volatile memory in 28nm high-K metal gate
Latest White Papers
- On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions