Boundary scan and JTAG emulation combine for advanced structural test and diagnostics
By Heiko Ehrenberg & Thomas Wenzel (Goepel Electronics Ltd.)
EE Times Europe (11/10/09, 04:02:00 AM EST)
While continuously improving IC and SOC technologies, higher clock rates, and more powerful processors are music to the design engineers' ears, the headaches of test engineers are getting worse and worse.
The ever decreasing test access was the worrying factor in the past, but a new problem arose in recent years with the dramatically increasing speed of the signal transmission.
The resulting failure phenomena and test access limitations have an inevitable impact on the efficiency and practicality of test strategies.
To read the full article, click here
Related Semiconductor IP
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
- Neuromorphic Processor IP
Related White Papers
- Signal Integrity --> LVDS extends utility of 1149.1 boundary scan test
- Processor Know Thyself: moving beyond on-chip JTAG emulation
- Boundary scan: Seven benefits
- ESC: Real-time analysis provides transport support for scan-based emulation
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS