Behavioral Design Drives Low-Power Silicon
By Brett Cline, Mike Meredith, Forte Design Systems
edadesignline.com (February 16, 2009)
Hardware designers adopt high level synthesis (HLS) for productivity benefits, and need the quality of results (QoR) to match or exceed what they can achieve with hand-constructed register transfer level (RTL) code. Historically, the most interesting QoR metrics have been limited mostly to circuit performance and chip area. As power consumption has risen in prominence as a dominant design criteria, it has also become a QoR metric of interest to HLS users.
Users of the new generation of high-level synthesis tools find that HLS can be used effectively to improve power consumption along with the other measures of circuit quality. Some of these improvements come from optimizations made by the HLS tool itself. Additional power reduction is achieved as a result of the inherent improvement HLS brings to the design flow, giving the designer the flexibility to easily experiment and identify the solution that consumes the least power.
High-level designers use a broad range of techniques to improve the overall power profile of their designs, including: power reduction by optimizing system architecture; micro-architecture exploration in the power dimension; high-level coding styles to reduce power; RTL coding styles for power optimization; and power optimizations made by HLS.
edadesignline.com (February 16, 2009)
Hardware designers adopt high level synthesis (HLS) for productivity benefits, and need the quality of results (QoR) to match or exceed what they can achieve with hand-constructed register transfer level (RTL) code. Historically, the most interesting QoR metrics have been limited mostly to circuit performance and chip area. As power consumption has risen in prominence as a dominant design criteria, it has also become a QoR metric of interest to HLS users.
Users of the new generation of high-level synthesis tools find that HLS can be used effectively to improve power consumption along with the other measures of circuit quality. Some of these improvements come from optimizations made by the HLS tool itself. Additional power reduction is achieved as a result of the inherent improvement HLS brings to the design flow, giving the designer the flexibility to easily experiment and identify the solution that consumes the least power.
High-level designers use a broad range of techniques to improve the overall power profile of their designs, including: power reduction by optimizing system architecture; micro-architecture exploration in the power dimension; high-level coding styles to reduce power; RTL coding styles for power optimization; and power optimizations made by HLS.
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- Behavioral Modeling Sets up ATM Design
- Memory Amnesia Could Hurt Low-Power Design
- Low-power SRAMs improve system picture
- From Behavioral to RTL Design Flow in SystemC
Latest Articles
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS