Automotive Architectures: Domain, Zonal and the Rise of Central
By Thierry Kouthon, Rambus
EETimes (February 16, 2022)
Electronics first appeared in cars in 1968 when Volkswagen installed an electronic control unit (ECU) in the VW 1600 sedan’s engine to help control fuel injection. Today, automotive electronics are ubiquitous, controlling or assisting with every aspect of the vehicle’s operation and performance. Electronics now account for over 40 percent of a new vehicle’s total cost, having grown from just 18 percent in 2000, according to Deloitte.
Integration of computing technology into every aspect of the car has transformed how automotive OEMs approach design, engineering and manufacturing. Up until the past decade, vehicle electronics used a flat architecture where embedded ECUs operated together in a limited way. The advancement toward connected cars and AVs led to a divergence in how carmakers approached the communication architecture of a vehicle’s electronics.
Concurrently, the introduction of sensors into the vehicle architecture further accelerated the need for greater computing power to process and analyze the resulting data. These new aspects of the vehicle’s brain led to differing design philosophies toward designing modern vehicles, from the domain architecture to newer zonal and central architectures.
To read the full article, click here
Related Semiconductor IP
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
- Neuromorphic Processor IP
Related White Papers
- The Rise of RISC-V and ISO 26262 Compliance
- An 800 Mpixels/s, ~260 LUTs Implementation of the QOI Lossless Image Compression Algorithm and its Improvement through Hilbert Scanning
- The pitfalls of mixing formal and simulation: Where trouble starts
- Stop-For-Top IP model to replace One-Stop-Shop by 2025... and support the creation of successful Chiplet business
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS