Two methodologies for ASIC conversion
Ron Wilson, EETimes
5/31/2011 2:30 PM EDT
ASIC vendor eASIC's announcement of a conversion path from their Nextreme structured devices to a fully cell-based ASIC offers an interesting opportunity to reflect on conversion methodologies. Comparing it to a recent discussion of the KaiSemi conversion flow, which takes a design from an FPGA to a cell-based ASIC, further illuminates some of the important choices that come up in reworking an existing design. The two approaches are conceptually similar, but practically quite different.
Structurally, the design problems the two companies face are similar. KaiSemi converts a working FPGA design into a cell-based ASIC design. Similarly, eASIC converts a Nexstreme or Nexstreme-2 structured device design - which may or may not have originated in an FPGA - into a cell-based design. Both strive to offer a turnkey service in which the customer has to understand very little of the ASIC process beyond RTL verification and timing.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Bluetooth Low Energy 6.0 Digital IP
- MIPI SWI3S Manager Core IP
- Ultra-low power high dynamic range image sensor
- Neural Video Processor IP
Related White Papers
- Structured ASIC Based SoC Design
- Build Complex ASICs Without ASIC Design Expertise, Expensive Tools - Take advantage of an architecture comparable to your original FPGA prototype design by migrating to a structured ASIC
- The Platform Based SOC Design that Utilizes Structured ASIC Technology
- NetComposer-II: High performance Structured ASIC Programmable NPU platform for layer 4-7 applications
Latest White Papers
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions
- CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions