Implementing analog functions in rugged, rad-hard FPGAs
Allan Chin and Luciano Zoso, Stellamar
EETimes (2/11/2013 2:21 PM EST)
FPGAs have already changed the cost/reliability paradigm for embedded systems in high-reliability applications, thanks to advances in hardness and power reduction. But on many embedded applications for high-reliability markets, designers depend on a number of peripheral analog components such as analog-to-digital and digital-to-analog converters to talk to the real world. Other system components such as phase-locked loops (PLLs) and DC/DC converters are usually required to complete a system design. These peripherals impact overall cost, size and reliability. Peripheral analog parts can also be challenging to work with and to source for radiation environments, as an example.
To further leverage the power of FPGAs, military-and-aerospace engineers are actively looking for ways to integrate many of these analog functions onto the FPGA. Synthesizable, digital IP cores that replace some analog functions now exist, allowing mil/aero designers to implement ADC, DAC, DC/DC controller and clock-multiplier functions in fully digital processes such as FPGAs. Not only does this new ability leverage the advantages of FPGAs, it also helps mitigate many challenges of using analog components in high-reliability applications.
To read the full article, click here
Related Semiconductor IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
Related Articles
- How FPGAs are breathing new life into the analog video format
- FPGAs solve challenges at the core of IoT implementation
- The common silicon issues in analog IP integration
- The Future of Embedded FPGAs - eFPGA: The Proof is in the Tape Out
Latest Articles
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
- In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events