Analog behavioral models reduce mixed-signal LSI verification time
By Takao Ito, Chief Specialist, Toshiba Corporation
Jun 22, 2007 (12:52 PM) -- Planet Analog
Figure 1a: CPU performance and simulation verification trend; taller (blue) bars are CPU performance, lower (yellow) bars are verification times
Figure 1b: Verification time trend
Jun 22, 2007 (12:52 PM) -- Planet Analog
Smaller process geometries are making it possible to take analog components off the board and incorporate them into the chip together with the digital portions of the designs, increasing the complexity of circuits. Even though there is a rapid increase in today's processor performance, simulation for full-chip verification is still taking a long time (Figure 1a and Figure 1b).
Figure 1a: CPU performance and simulation verification trend; taller (blue) bars are CPU performance, lower (yellow) bars are verification times
Figure 1b: Verification time trend
Current methodologies are no longer sufficient or acceptable, so new verification methods are needed.
To read the full article, click here
Related Semiconductor IP
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- FH-OFDM Modem
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- PQC CRYSTALS core for accelerating NIST FIPS 202 FIPS 203 and FIPS 204
- USB Full Speed Transceiver
Related White Papers
- Efficient Verification and Virtual Prototyping of Analog and Mixed-Signal IP and SOCs Using Behavioral Models
- Mixed-signal SOC verification using analog behavioral models
- Reuse of Analog Mixed Signal IP for SoC Design: Progress Report (Cadence Design Systems)
- Analog & Mixed Signal IC Debug: A high precision ADC application
Latest White Papers
- FastPath: A Hybrid Approach for Efficient Hardware Security Verification
- Automotive IP-Cores: Evolution and Future Perspectives
- TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models