Algorithmic synthesis for video post-processor design

By Pradeep Thiruchelvam, Synfora, Inc.
edadesignline.com (December 09, 2008)

Introduction

With growing consumer demand for faster, cheaper and more complex devices, designers face constant pressure to meet time-to-market deadlines and financial constraints. The need to integrate ever more functionality into a product leads to a growing number of algorithms, all of which must be implemented in the SoCs that drive the product. A designer's chief challenge today is to execute these highly complex algorithms in hardware as rapidly as possible, while meeting aggressive high-performance and low-power goals. As a result, a disproportionate amount of design time is spent on hardware implementation rather than algorithmic innovation.

This article describes how ST Microelectronics used Algorithmic Synthesis to design a video post-processor, with the goals of improving project time and design flexibility, without compromising performance and power targets.

Algorithmic Synthesis offers the solution

Engineers can reduce project time and costs significantly if they elevate the design abstraction to an algorithmic level. Algorithmic synthesis (AS) technology allows the creation of complete application engines directly from sequential, untimed C algorithms. This enables the designer to explore multiple algorithms and implementation alternatives with different performance, area and power (PPA) profiles quickly, to find an optimal design and build the hardware automatically.

ST used PICO Express algorithmic synthesis to design a multi standard video post-processor (VPP), an integral part of a multi-standard video CODEC that comprises deblocking and deringing functions. The VPP was selected as a representative example to implement using AS, because it offered the possibility of directly comparing the resulting PPA and time taken with a hand-designed block.

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