Address jitter and noise more effectively with DDR4, part1
Perry Keller, Agilent Technologies
EETimes (5/21/2013 12:15 PM EDT)
The latest generation of DDR memory, DDR4, doubles the speed of the current generation of DRAMs, DDR3, with end-of-life data rates of 3.2 GT/s. Compared to the first generation of DDR memory, which started out at 200 MT/s, DDR4 will be running almost 16 times faster. When DDR was first introduced thirteen years ago, the typical semiconductor feature size was 130 nm and a 2.5-V operating voltage was the standard. Now, devices promise to approach 14 nm feature sizes and 1 V operating voltages. The DRAM specs need to keep up. As DDR3 speeds approached 1600 MT/s and the DRAM data valid windows shrank from 800 ps at 600 mV to less than 60 ps at 270 mV, the DDR4 standards development team recognized the need to take a new approach.
To address the challenges posed by higher data rates, the DDR4 specification (JESD79-4) adopts several proven strategies from modern high-speed serial specifications like PCI Express and Super Speed USB. In fact, the DDR4 specification takes things one step further by providing a way for designers to allocate the system timing and noise budget between the controller, memory interconnect and the DRAM that is difficult, if not impossible, to accomplish with other high speed-interfaces.
To read the full article, click here
Related Semiconductor IP
- DDR4 IO for memory PHY, 3200Mbps on SMIC 40nm
- DDR5 & DDR4 COMBO IO for memory controller PHY, 4800Mbps on TSMC 12nm
- DDR4 & LPDDR4 COMBO IO for memory controller PHY, 3200Mbps on TSMC 22nm
- DDR3 and DDR4 Controller and PHY on TSMC 12nm
- Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
Related White Papers
- Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
- Using Memory More Effectively in NPU Designs
- Overcome signal attenuation, noise and jitter interference challenges in USB 3.0 system design
- Supply Noise Induced Jitter - Don't Let it Kill your Chip
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design