Yield challenges require new DFM approach

The phrase design for manufacture (DFM) refers to a variety of techniques used during IC design so as to facilitate its being manufactured. Meanwhile, the term “yield” refers to the number of die that work as a percentage of the total number of die on the silicon wafer.

The phrase design for yield (DFY) refers to any techniques used to improve the yield of a particular device. In reality, these concepts and techniques are so intertwined that it is becoming common to consider them as being a single DFM/DFY entity.

Until recently, design engineers had relatively little concern with regard to manufacturability or yield. With the current 90 nanometer technology node, however, manufacturing and yield issues are being pushed upstream into the design process, because these factors are strongly design dependent and are affected by how the design is laid out. If these problems are not addressed, it may not be possible to achieve economically viable yields at the forthcoming 65 and 45 nanometer technology nodes.

There have been some efforts with regard to DFM/DFY random (statistical) yield. To date, however, almost all of the focus on systematic yield issues has been in the area known as front end-of-line (FEOL). This encompasses the diffusion, poly, and contact layers forming the transistors — that is, everything below metal layer 1.

At the 90 nanometer node, however, the routing in the metal layers is becoming a significant systematic yield issue which no one has addressed thus far. As we move to the 65 nanometer node and below, routing will become a major yield limiter for designs.

This paper first introduces the DFM/DFY problems associated with technology nodes of 90 nanometers and below. Next, the paper considers the traditional split between design and manufacturing coupled with the inadequacies of current DFM/DFY techniques. Finally, the paper discusses the way in which these problems can be addressed by means of next-generation routing technologies.

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