The Secret to Building IP at the Cutting Edge
By John Maneatis, True Circuits
At 7nm and beyond, the cost and time to develop IP is very high. To gain a suitable return, it's critical to have an efficient design methodology that produces a portfolio of attractive solutions in many process variants, metal stacks, Vt selections, and even completely different foundries. TCI employs a range of fascinating techniques, from building robust circuits, to using proprietary extensions of CAD tools to creating designs and deliverables from one, universal database. In this presentation John will explain the engineering behind a highly automated CAD flow that enables TCI to maximize IP consistency, quality and reuse.
AUTHOR:
John Maneatis is TCI's co-founder, President, and Chief Technologist. He holds a B.S. degree in Electrical Engineering and Computer Science from U.C. Berkeley, and M.S. and Ph.D. degrees in Electrical Engineering from Stanford University. John has almost 30 years of experience in analog and digital circuit design and is world renowned for his work in the area of Phase-Locked Loop design. He has given multiple authoritative presentations at the IEEE ISSCC and regularly presents at industry trade shows on topics of analog design, circuit simulation and CAD development.
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related White Papers
- At the edge of data processing
- The Answer to Non-Volatile Memory Security Issues at Advanced Nodes: Go Volatile!
- Enabling AI Vision at the Edge
- Paving the way for the next generation of audio codec for True Wireless Stereo (TWS) applications - PART 5 : Cutting time to market in a safe and timely manner
Latest White Papers
- Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- 40G UCIe IP Advantages for AI Applications
- Recent progress in spin-orbit torque magnetic random-access memory
- What is JESD204C? A quick glance at the standard
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience