The Secret to Building IP at the Cutting Edge
By John Maneatis, True Circuits
At 7nm and beyond, the cost and time to develop IP is very high. To gain a suitable return, it's critical to have an efficient design methodology that produces a portfolio of attractive solutions in many process variants, metal stacks, Vt selections, and even completely different foundries. TCI employs a range of fascinating techniques, from building robust circuits, to using proprietary extensions of CAD tools to creating designs and deliverables from one, universal database. In this presentation John will explain the engineering behind a highly automated CAD flow that enables TCI to maximize IP consistency, quality and reuse.
AUTHOR:
John Maneatis is TCI's co-founder, President, and Chief Technologist. He holds a B.S. degree in Electrical Engineering and Computer Science from U.C. Berkeley, and M.S. and Ph.D. degrees in Electrical Engineering from Stanford University. John has almost 30 years of experience in analog and digital circuit design and is world renowned for his work in the area of Phase-Locked Loop design. He has given multiple authoritative presentations at the IEEE ISSCC and regularly presents at industry trade shows on topics of analog design, circuit simulation and CAD development.
Related Semiconductor IP
- Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
- PUF FPGA-Xilinx Premium with key wrap
- ASIL-B Ready PUF Hardware Premium with key wrap and certification support
- ASIL-B Ready PUF Hardware Base
- PUF Software Premium with key wrap and certification support
Related White Papers
- Enabling AI Vision at the Edge
- Paving the way for the next generation of audio codec for True Wireless Stereo (TWS) applications - PART 5 : Cutting time to market in a safe and timely manner
- Stop-For-Top IP model to replace One-Stop-Shop by 2025... and support the creation of successful Chiplet business
- MIPI in next generation of AI IoT devices at the edge
Latest White Papers
- e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
- How to design secure SoCs, Part II: Key Management
- Seven Key Advantages of Implementing eFPGA with Soft IP vs. Hard IP
- Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU
- Data Movement Is the Energy Bottleneck of Today’s SoCs