Reuse of system-level model key

Reuse of system-level model key
By Frank Schirrmeister, Director of Business Development, Sarah Lynne Cooper, Product-Marketing Manager, Cadence Design Systems Inc., San Jose, Calif., EE Times
January 3, 2002 (5:43 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011205S0047

The consumerization of electronics is driving technology convergence to ready products for wireless communications or additional multimedia capabilities. As a result, system-on-chip designs have become so complex that they can no longer be managed by just one architect: There's simply too much data, coming from too many sources, influencing design decisions. Designs that may once have been dominated by DSP now require significant control capabilities in order to satisfy consumer demands.

Simply adding resources to design teams is not the appropriate way to respond to the challenge. Rather, the mind-set of designers has to be addressed as well. Design teams have to buy into the fact that other team members, or other companies, can deliver trustworthy intellectual property that can be reused without modification.

Communication within and between design teams becomes key for design in the communications space. Three related issues can acce lerate design time, but they are often overlooked or unknown by design teams.

First, within an organization, vertical communication among teams performing verification of the RTL implementation of DSP designs can lead to more efficient reuse of data. System-level design teams create models at a higher level of abstraction, which can serve as a golden model for functional verification.

Second, reference libraries among organizations and companies should dramatically cut the time it takes to enter new markets. Instead of starting from scratch, today's system-level tools typically come with libraries, which serve as reference for design and verification.

Finally, the need for data exchange leads to methodology enhancements, which can be seen in the adoption of platform-based design. Systems houses are able to choose from a variety of "base functions," which are delivered as intrinsic functionality to an existing platform.

For example, MPEG decoding becomes a nondifferentiating c ommodity in the era of platform-based designs for set-top boxes, so design teams expect different implementation options from which to choose (i.e., hardware, software or intelligent hardware-software combinations).

Reuse of system-level models within a design team for hardware verification and implementation facilitates communication between system engineers and hardware engineers, who often have fundamentally different skill sets. A key problem with current approaches is that the techniques used for implementation at the RTL signal level are based on hardware-description languages (Verilog, VHDL or SystemC-RTL), while system-level designers use more abstract descriptions, in C, C++ or specialized graphical languages like SDL. Design teams are connecting ad hoc design flows through such techniques as programming language interfaces to the HDL representation. It is a tedious, nonrepeatable process.

New tools and methods allow designers to develop graphical and hierarchical executable specific ations of DSP and communications systems in C++, often using reference libraries based on standards. Algorithms can be designed and verified at floating-point and fixed-point levels of abstraction and refined to the implementation level. The implementation design teams can use the models as simulation references for hardware and software implementation. Testbenches modeling the system environment allow functional verification at a very early stage in the design flow and can be reused as "golden testbenches" in functional verification throughout the design process.

While tool-supported flows constrain the content of C or C++ and require certain coding styles, they significantly increase productivity because statically scheduled data flow code with a defined type of system can be simulated much faster than hand-coded, free-form C++. Design issues that arise from using such a design process are incompatibilities between the system designer's intent and the hardware designer's implementation.

St andards are developing worldwide at incredible speed, making it difficult to keep track of the latest developments across all application areas. Typically, only the first-tier market leaders in each application segment can afford to drive standards and invest the resources required to take the lead in new markets. When faced with entering new or incremental markets and application areas, the traditional approach for acquiring experience is to charter design teams to analyze new requirements and to start basic developments. Smaller companies are often targeted by bigger ones for knowledge, experience and resources.

Deciphering standards

A typical standard for a decoding algorithm like H.263, for low-bit-rate video encoding and decoding, runs in the hundreds of pages. Understanding the standardized algorithms just by reading the spec is a time-consuming and difficult process. Standards typically cover a range of options, and it is often difficult to determine which configurations will fi nd best market acceptance. Executable reference models clearly model those configurations and ease the choice of implementation for the design team.

Standards committees are adopting approaches to base their development on standard languages or popular tools. For example, in the telecommunications segment the ISO-standard Specification Description Language (SDL) is fairly well-established for descriptions of communication protocols. Further, C+-based reference models representing an executable reference are often available. And tool providers may include library reference models of the most popular developments as part of their solutions.

Motorola's Semiconductor Products Sector was poised to introduce new-generation communications technology and faced the challenge of securing its position in the evolving 3GPP market. Achieving that goal would require the development of system solutions for the Universal Mobile Telecommunication System (UMTS) standard. Using prequalified intellectual propert y, Motorola performed testing and the incorporation of its own specific IP. The company met the schedule deadline using fewer resources, with a reduced risk of the product's failing in field tests.

Key players in the electronics design chain are increasingly focusing on their core competencies. For example, Ericsson now outsources cell phone manufacturing and has entered a joint-venture agreement with Sony to develop and deliver next-generation handsets. The design chain interaction between semiconductor houses (such as Texas Instruments or Philips Semiconductors) and systems integrators (such as Sony, Ericsson and Nokia) requires new levels of communication. To address the ever-increasing costs of verification masks and production, the industry is turning to platform-based design methodologies. Platform systems-on-chip offer enough flexibility-via software or programmable hardware-to serve a range of derivatives within a given application domain. Examples in the communications domain are the Texas I nstruments Omap, Infineon MGold and ARM PrimeXsys platforms.

In the era of platform-based design, system integrators can expect basic functionality to be part of the platform enabled by the semiconductor provider. For example, PacketVideo's MPEG-4 offerings are available and tested on the Omap platform.

In the future, communicating architectural options to systems houses and articulating system-level requirements to the semiconductor provider will depend on efficient tool support. With a tool-based approach, the systems house can define its differentiating algorithmic requirements and execute them on a virtual model of the platform architecture to assess optimal system balance.

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