Multicore SoCs change interconnect requirements
Greg Shippen, Freescale Semiconductor
EE Times (10/20/2008 12:01 AM EDT)
The recent appearance of multicore system-on-chip (SoC) devices has rearranged the boundaries among silicon devices, boards and subsystems. This trend has led to significant changes in chip-to-chip and board-to-board interconnect requirements. Are existing standards-based interconnects ready for this transition?
With the introduction of the microprocessor in the 1970s, simple computing systems were constructed on a single board using a discrete processor, memory controller and I/O interface device. Board-level buses connected the devices; when higher performance was desired, multiple boards were assembled together. Backplanes provided communication between cards using a system-level bus.
These board- and system-interconnect protocols were proprietary. Over time, closed protocols gave way to standardized protocols such as Ethernet, PCI Express or RapidIO.
EE Times (10/20/2008 12:01 AM EDT)
The recent appearance of multicore system-on-chip (SoC) devices has rearranged the boundaries among silicon devices, boards and subsystems. This trend has led to significant changes in chip-to-chip and board-to-board interconnect requirements. Are existing standards-based interconnects ready for this transition?
With the introduction of the microprocessor in the 1970s, simple computing systems were constructed on a single board using a discrete processor, memory controller and I/O interface device. Board-level buses connected the devices; when higher performance was desired, multiple boards were assembled together. Backplanes provided communication between cards using a system-level bus.
These board- and system-interconnect protocols were proprietary. Over time, closed protocols gave way to standardized protocols such as Ethernet, PCI Express or RapidIO.
To read the full article, click here
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
Related Articles
- Using dynamic run-time scheduling to improve the price-performance-power efficiency of heterogeneous multicore SoCs
- Multicore microprocessors and embedded multicore SOCs have very different needs
- Build low power video SoCs with programmable multi-core video processor IP
- Using drowsy cores to lower power in multicore SoCs
Latest Articles
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension
- ioPUF+: A PUF Based on I/O Pull-Up/Down Resistors for Secret Key Generation in IoT Nodes
- In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss
- David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
- RoMe: Row Granularity Access Memory System for Large Language Models