Using drowsy cores to lower power in multicore SoCs
Cody Croxton, Ben Eckermann and David Lapp
EETimes (6/29/2011 2:18 PM EDT)
Freescale engineers describe a cascading power management technique that steers tasks to a smaller number of cores during non-peak activity periods so that the idle cores can enter a minimal-power or “drowsy” state. Multicore processing has enabled higher and higher levels of processing capability, but with a price: higher levels of power consumption. Cascading power management is a technique that steers tasks to a smaller number of cores during non-peak activity periods so that the idle cores can enter a minimal-power or “drowsy” state.
When packet traffic increases again, the technique allows a rapid return to fully loaded conditions. Cascading power management is not simply a power-saving technique; it is also a workload management technique that distributes packet processing in a more efficient way.
To read the full article, click here
Related Semiconductor IP
- Temperature Glitch Detector
- Clock Attack Monitor
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
Related White Papers
- How NoCs ace power management and functional safety in SoCs
- Get the right mix when integrating Power Management Solutions into SoCs
- Using dynamic run-time scheduling to improve the price-performance-power efficiency of heterogeneous multicore SoCs
- Defining standard Debug Interface Socket requirements for OCP-Compliant multicore SoCs: Part 1