Multi-chip architectures partition H.264 tasks to achieve high-quality video

Video is becoming all-pervasive, and consumers want it in all types of devices with various levels of video quality. For some devices, such as cell phones or portable music/video players, a single digital signal processor (DSP) can handle all video-processing tasks and meet tight cost budgets.

For high-quality applications such as high-definition (HD) TV or video teleconferencing, however, the processing requirements are beyond those of any single device on the market today. Here multi-chip systems--whether made of multiple DSPs or DSP and FPGA combinations--can implement high-quality video without being excessively complicated or expensive. To make an intelligent decision as to how to partition the tasks among processors requires designers to consider not only resources available in the devices but also to examine the algorithms.

H.264 (MPEG-4 AVC) has emerged as the industry's hot new video codec. It produces MPEG-2 quality video with roughly half the number of bits or generates far higher quality with the same number of bits. These benefits demand significantly more processing power than an MPEG-2 codec.

Furthermore, the computational requirements are not fixed by the H.264 codec standard. They depend on a wide range of variables determined by the codec implementer including the resolution and frame rate, the output bitrate, the H.264 encoder profile, and specific features such as the search range, search algorithm, search partitions, refinement and number of reference frames. These parameters all have an effect on the perceived video quality. Thus, the computational requirements of a system are directly influenced by the video quality requirements and can vary substantially between systems that nominally use the same codec.

To read the full article, click here