How SLEC improves functional verification
Leveraging System Models for RTL Functional Verification using Sequential Logic Equivalence Checking (SLEC).
By Anmol Mathur, Calypto Design Systems
edadesignline.com (January 23, 2009)
Design teams commonly use system models for verification. System models have many advantages over register transfer level (RTL) code for verification, notably, because of their ease of development and runtime performance. The ability to leverage the system-level verification to create functionally correct RTL code has challenged many a design team until now. A methodology known as Sequential Logic Equivalence Checking (SLEC) has the unique capability to formally verify RTL implementations against a specification written in C/C++ or System C.
This article will describe the system-level design flow of a commercial graphics processing chip. In this flow, system models have been developed to validate the arithmetic computation of video instructions and then used to verify the RTL implementation using the SLEC methodology.
To read the full article, click here
Related Semiconductor IP
- NPU IP Core for Mobile
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
- HYPERBUS™ Memory Controller
- AV1 Video Encoder IP
Related White Papers
- Shifting from functional to structured techniques improves test quality
- How formal verification saves time in digital IP design
- Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP
- SoC Functional verification flow
Latest White Papers
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design
- CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
- Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions
- Automating NoC Design to Tackle Rising SoC Complexity