FPGAs: Embedded Apps : CPLDs become heart of scalable storage system

CPLDs become heart of scalable storage system
By EE Times
July 1, 2002 (10:37 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020628S0104

Rajiv Nema, Senior Product Marketing Manager, Cypress Semiconductor, Inc., San Jose, Calif., Andrew Randall, Chief Engineer, Nexsan Technologies, Inc., Woodland Hills, Calif.

The following options were considered for the design of the new controller for these products: an off-the-shelf IC which would allow low cost and quick time-to-market, an ASIC which would lower overall cost at high volume, and programmable logic devices such as FPGAs and CPLDs which would offer flexibility of implementation.

The off-the-shelf ATA chips that were available were mostly designed for use on PC motherboards and therefore were not satisfactory. Some of the parts did not even check for incoming PCI parity, a situation that is not acceptable in a RAID solution. These off-the-shelf solutions offered a very similar feature set, for example, 32bit, 33MHz PCI, and small data FIFO (typically 128-256 bytes)

The 32-bit, 33MHz PCI generally delivers about 80 to 100 Mbytes/second sustained transfer rate but the base goals for Nexsan's RAID product were way above that. With this in mind, it was clear that an off-the-shelf solution was unlikely to make the stated performance or scalability goals.

ASIC designs offer a tantalizing prospect - lower overall cost at high volume, high performance due to the custom design and no programming overhead. However, the irony is that the advantages can become disadvantages depending on your project. For instance, a very complex design with tight deadlines to production may not be a good ASIC candidate.

Although ASICs are known for their low-cost promise, they risk expensive Non-Recurring Engineering (NRE) fees that may become uncontrollable. However, this was not the deciding factor for Nexsan. The major problem they encountered with an ASIC solution was that the ATA specification was about to incorporate some new features and there was no way of performing interoperability tests before ASIC sign-off. Therefore an ASIC was unsuitable for this project at that time and using programmable logic devices (PLDs) would have been the next best option.

FPGAs are offered in a wide density range, from a few thousand gates to several million gates. The FPGA architecture incorporates high flip-flop to logic ratio making it ideal for register intensive applications. Also, the FPGA architecture is more granular compared to CPLD architecture making it suitable for designs with large number of simple blocks with few number of inputs. On the other hand, CPLDs are ideal for complex blocks with a large number of inputs.

FPGAs and CPLDs are complimentary in architectures; therefore for any design project that may require programmable logic, both these options must be evaluated to determine which one is a better fit for your needs.

Due to the granular architecture and segmented routing of FPGAs, it is difficult to predict the speed performance of a design until it is targeted in the software. Moreover, a last-minute minor modification to the design can sometimes cause a complete refit resulting in undesirable timing.

CPLD over FPGA

A considerable amount of time was spent in finding a leading FPGA device with a price and performance range comparable to that of a CPLD device. The main observation was that the same design that fit into a 100K gate CPLD (Cypress Semiconductor's Delta39K CPLD) required a 150K gate FPGA. Also, a number of Input-Output (I/O) pins offered on the CPLD were significantly higher than those on the targeted FPG A. Although the FPGA had plenty of spare gates, the Nexsan design didn't use them. For this particular design, the trade-off of logic density against I/O pins favored a CPLD over FPGA.

In addition, FPGAs invariably require one or more configuration PROM, depending on the size of the FPGA used. This results in increased board space, board layout complexity, cost and bill-of-material (BOM).

CPLDs, with their coarse-grain architecture and dedicated routing, offer the advantage of predictable timing and ease-of-use. Performance of a design can be estimated by looking at the datasheet parameters. Additionally, the embedded features like multi-port memories, FIFOs, Phase Locked Loops (PLLs) make them a compelling alternative to FPGA.

Nexsan chose the Delta39K CPLD because the design team needed a device with embedded dual-port RAM to implement FIFO and single port RAM for scatter gather tables and configuration registers. For the concurrent operation and low overhead, an integrated independ ent DMA controller for every protocol engine was required, increasing the requirement for a single port RAM still further.

In addition, when the design was first completed in early 2001, 48-bit Logical Block Address (LBA) support would need to be added into the design later — therefore, the CPLD chosen had to allow for in-system reprogramming and configuration from the CPU. Therefore, a re-configurable CPLD was required.

The CPLD devices cover only a subset of densities for the latest FPGA families. However, they do offer a compelling alternative in density range, matching FPGAs. CPLDs can sometimes be more expensive than their FPGA counter parts at the same density. But if the inherent CPLD advantage of predictable timing and hence quicker design verification and timing closure allows you to get to market several months earlier, the resulting revenue earned is well worth the extra R&D money spent.

For the eight-drive unit three 39K100 devices were employed. The first two devices were standard three port PCI-ATA controllers and the third device incorporated two ATA channels and some additional power control, sense logic and inter-board communication logic for active-active configurations. The 14-drive unit used five 39K100 devices, four of these contained the standard code and the fifth device contained the modified code for active-active control.

The collaboration between Nexsan and Cypress produced a product design that not only met the requirements, but has been proven by market success.

The Delta39K devices have proved to be a reliable and stable platform. The design has been modified to incorporate 48-bit LBA support and the ATA protocol engine has been enhanced to include more features, further lowering the CPU overhead in the Nexsan system. These design changes have been achieved with ease as the predictable nature of CPLD devices makes such changes fairly painless.