How to build a better DC/DC regulator using FPGAs
Adam P. Taylor, EADS Astrium
EETimes (11/2/2011 3:07 PM EDT)
Designers traditionally build switch-mode DC/DC converters using analog components (bespoke ICs, operational amplifiers, resistors, capacitors and the like) to control the feedback loop and to generate the pulse-width modulation required for switching. When using analog components like these, you must consider a number of factors, taking tolerances, electrical stresses, aging drift, and temperature drift into account to ensure the stability of the design. Now, the availability of affordable low-powered FPGAs coupled with analog-to-digital converters allows the FPGA to replace the traditional analog approach.
DC/DC converters are designed in one of four main topologies: buck (step-down), boost (step-up), inverting (converting a positive input to a negative output), and SEPIC (single-ended primary inductor converter). SEPIC devices maintain a constant output voltage, stepping the input voltage up or down depending upon the circumstances. For this reason, they are a popular choice for battery-based applications.
To read the full article, click here
Related Semiconductor IP
- DC/DC Buck Regulator
- DC/DC Buck Regulator
- 5A DCDC, 0.60...1.43V switching regulator using COT switch mode, Vin=4.25...15V
- DC/DC - Audio Grade Buck Regulator - TSMC 0.18um
- DC/DC - Audio Grade Buck Regulator
Related White Papers
- How to simplify switch-mode DC-DC converter design
- PowerSoC solves switch-mode DCDC noise and space issues
- Time is money! A quick fix for those pesky FPGA design errors
- How to use the CORDIC algorithm in your FPGA design
Latest White Papers
- Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- 40G UCIe IP Advantages for AI Applications
- Recent progress in spin-orbit torque magnetic random-access memory
- What is JESD204C? A quick glance at the standard
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience